Challenge:
Most of the signal/image processing applications require
the reconstruction of acquired data to allow further analysis of
this data on a computer. The challenge is that the physical
acquisition modalities are not in the Cartesian space but rather
complex geometries, e.g. cone-beam Computed Tomography (CT),
combined with very large sizes of the acquired data and noisy
sampling conditions. In addition very fast reconstruction
(real-time) is often required.
Our solution:
We have designed a novel algorithm for the reconstruction
of large multidimensional data (3D/4D/5D and possibly higher
dimensions) on arbitrary grids with high
quality. As published in leading journals, our implementation,
using MultiCore and GPGPU (which are typically more than 20 times
faster) beat the best published implementations in
terms of image quality and reconstruction speed.
Example:
Here we present an example of reconstruction of a high resolution CT
dataset.
Figure 1. Reference CT dataset defined on a grid of 400x400x400 voxels
Figure 2. Cone-beam CT reconstruction
Challenge:
Conventional medical imaging techniques often involve dangerous
radiation or require large initial investments and
servicing/maintenance costs (e.g. MRI) affordable only for large
institutions. In vivo fluorescence imaging in humans is a new
imaging modality which breaks the aforementioned limitations and can
be performed without ionizing radiation, is relatively inexpensive,
portable and therefore, opens the doors to the use in smaller
medical organizations including private practices. For making 3D
optical fluorescence tomography in humans available multiple
technical problems have to be resolved, including development of
advanced reconstruction algorithms, high-performance
software/hardware for solving large underlying computational
problems, high-performance optical sub-system and specialized
fluorescence materials suitable for this type of imaging.
Our solution:
Based on the experience with our 2D fluorescence imaging system for
animals we are now extending the system to a next generation
suitable for in vivo 3D fluorescence tomographic imaging in humans.
The ongoing development is being performed within a consortium of
University Hospital Basel and ETH Zurich.
Challenge:
Modern medical imaging equipment produces very large size
image data, often in 3D, 4D, or 5D formats, and requiring large
amounts of data storage and broadband transmission infrastructure.
Although the data are often highly coherent in multidimensional
space, typical image compression algorithms loose such
multidimensional coherence. This leads, at a prespecified
compression level, to significant image quality degradation, or at a
prespecified image quality, to unnecessarily large datasets.
Our solution:
We developed a novel compression algorithm, using leading edge
3D/4D/5D wavelet technology, exploiting multidimensional data
coherence, and featuring a multidimensional tree structure. This
novel compression algorithm yields ultrahigh compression ratios with
excellent image quality retention for 3D, 4D (and 5D) data. In a
first class scientific journal, we could show that our algorithm
yields significant improvements compared to the state of the art in
terms of compression ratios and reconstructed image quality. As this
approach is fully parallelizable and can even be executed on general
purpuse graphic card hardware (GPGPU) or field-programmable gate
arrays (FPGA), it is very useful to reduce hardware constraints on
storage and network infrastructure in high density, multidimensional
imaging for storage and data transfer. Using this approach, you can
achieve more with a given hardware; inversely, for a given task,
your hardware requirements are significantly reduced.
Challenge:
Most embedded signal/image processing systems require developers to
implement customized hardware to meet the strict size, performance,
power consumption and time-to-market requirements. The increasing
capability and configurability make FPGAs become a common platform
for developing customized hardware. However, the manual hardware
development process and the communication overhead between
application and hardware developers extends the development time,
and postpone the system’s time-to-market. To accelerate the
FPGA-based system development process, it is necessary to build a
system design environment that can support automatic system
construction, which includes generating target hardware circuit and
software images. The main challenge in building such a system design
environment is to bridge the big semantic gap between the
application and the hardware specifications.
Our solution:
We have implemented a system design environment for automating the
design of complete, genuinely parallel, high-performance streaming
systems on FPGA. Our design environment offers an automatic mapping
from an application implemented in a high-level language to the
target multicore hardware architecture on FPGA, while avoiding deep
understanding of a specific hardware and limiting the
hardware-related work for the application developer which in turn
accelerates the development and decreases the time-to-market. The
functionality and portability of the implemented hardware and
software layers of the used system design environment allow the
development of various data streaming applications on various FPGAs
such as Virtex and Spartan series from Xilinx.
Example:
Here we present an example of an ECG signal analysis system
implemented in our system design environment.
Figure 3. Block diagrams, (a) The ECG application; (b) The target platform
Challenge:
For increasing the performance of parallel MultiCore data processing
applications running on FPGAs it is desirable to have an additional
level of parallelism such as SIMD (Single Instruction Multiple Data)
available on each processing core. The main challenge of
implementing this vector processing functionality is in achieving
the highest possible performance without paying too much in terms of
the usage of FPGA resources.
Our solution:
We extended our system design environment with an implementation of
a fixed-point/floating point vector processing unit with
configurable number of vector elements, which can be optionally
chosen to expand the functionality of available multiple processing
cores.
Challenge:
FPGAs are always considered as non-power-efficient devices. The main
challenge in achieve power efficiency on FPGAs is to properly
partition the circuitry into asynchronous components and allow
programmers to control the mode of the components, for example,
sleeping or busy modes.
Our solution:
Within our system design environment we have implemented a portable,
configurable hardware and software components which enable the
design of power-aware applications on FPGA. Our preliminary results
show that our implementation allows up to 50% decrease of power
consumption.